Parasitic Capacitance Extraction Method by Metal-Gate-Coupling Structure for Non-Planar Transistors
碩士 === 國立清華大學 === 電子工程研究所 === 103 === To scale CMOS field-effect transistors (FETs) well into the sub-20nm region, multi-gate structure, such as, FinFET is adapted as the mainstream technology solution for the suppression of short channel effects and maintaining high-gate control ability. However, d...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2015
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| Online Access: | http://ndltd.ncl.edu.tw/handle/00269163125748936394 |