Fabrication of fast program/erase charge-trapping non-volatile memory using barrier-engineered dielectric and ultra-thin epi-like Si channel

• Main Authors: Wu, Ssu-yu, 吳思諭
• Other Authors: 吳孟奇
• Format: Others
• Language: en_US
• Published: 2014
• Online Access: http://ndltd.ncl.edu.tw/handle/uf86ga

碩士 === 國立清華大學 === 電子工程研究所 === 103 === In this thesis, Pulse Laser Crystallization/green nanosecond laser spike annealing technique is applied to fabricate crystallized active layer channel, which consists of high quality poly-silicon material known as epi-like Si, of non-volatile memory (NVM). This technique turns amorphous silicon thin film into epi-like Si with 1000nm grain size, followed by CMP to reduce surface roughness from 37A to 5A, and ultra-thin (13nm) planarized epi-like silicon thin film channel is obtained. Due to the low thermal budget (< 450℃) of the process, when integrated with metal gate, high performance non-volatile memory can be developed with subthreshold swing below 170 mV/Decade and high on/off ratio beyond 10^6. In addition, with inductively coupled plasma chemical vapor deposition system (ICPCVD) at low temperature process and depositing high-κ material (Al2O3) with ALD, low defect and high quality dielectric can be obtained. By applying barrier engineering technique to gate dielectric, metal gate NVM comprised of oxide / oxide / (Al2O3/) oxide is successfully demonstrated, abbreviated as VARIOT MONOS NVM, and thus performance and reliability is greatly improved. With program voltage at 7V and 9V, the device exhibits 1.2V and 1.9V memory window with 50ns and 100ns pulse width, respectively, and good data preservation of charge loss after 10 years is estimated to be within 30% as well. Besides, in terms of endurance, good electrical characteristic is retained after 1000 program/erase cycles. Therefore, barrier engineering technique having superiority in performance and reliability must be a successful modification technique, and can be developed into promising Stacking Non-Volatile Memory.