Optimization Techniques for PCB Escape Routing and Double Patterning-Aware Chip Routing
博士 === 國立清華大學 === 資訊工程學系 === 103 === As the technology node scales down to nanometer range, packages and chips both face many challenges in physical design and manufacturing process. With the increasing complexity of circuit design in recent years, package pin assignment and printed circuit board (P...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2015
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| Online Access: | http://ndltd.ncl.edu.tw/handle/04235751450578301148 |