A Variable-precision Architecture for Special Function and Floating-point Multiply-add-fused Operation

• Main Authors: Li-wei Hsu, 徐立緯
• Other Authors: Shiann-Rong Kuang
• Format: Others
• Language: zh-TW
• Published: 2015
• Online Access: http://ndltd.ncl.edu.tw/handle/9u4ku9

碩士 === 國立中山大學 === 資訊工程學系研究所 === 103 === This thesis presents a variable-precision floating-point arithmetic unit based on IEEE-754 single precision floating standard. This arithmetic unit combines special function interpolator and floating-point multiply-add-fused. The arithmetic unit provides Exponential, Logarithm, Reciprocal, Reciprocal square root, multiplication, addition, and multiply-add operations. Each operation also provides different precision mode. Its hardware architecture is a pipeline design, which can be used in DSP, GPU and so on. 　　With computing quadratic polynomial, special function interpolator obtains the approximate value which is close to the objective function. Coefficient of quadratic polynomial is computes by using piecewise minimax approximation, and stored in the table for searching the coefficient when computing quadratic polynomial. The floating-point MAF combines the floating-point multiplication and floating-point addition into a single hardware, which is used to execute the multiply and accumulate like A+B×C. When executing multiplication, the floating-point MAF aligns the decimal point of the addition parallelly to increase the performance. 　　In other words, the concept of the variable-precision floating-point arithmetic unit is that it can decrease power consumption by executing the low precision operation when the user doesn`t need the high precision result. Because the higher precision operation uses more cells than the lower precision. Variable-precision floating-point arithmetic unit uses the same hardware to execute the different precision operations, and one proper precision mode can be selected according to user’s requirement without adding extra hardware for lower precision mode. For example, the original arithmetic unit is IEEE-754 double precision standard hardware. If only the data compliant with IEEE-754 single precision standard are needed, it would cost much more power consumption when we use the double precision arithmetic unit. Therefore, variable-precision floating-point arithmetic unit can save the unnecessary power by executing both the single and the double precision operations with the same hardware. 　　When execution non-highest precision operations, the clock-gating cells and latches are used to close the unnecessary cells to decrease the power consumption of the non-highest precision operations. Because the special function interpolator can only execute one of the four operations to reduce the dynamic power consumption of the tables for other three operations. Therefore, we can still decrease the power consumption even the highest precision operation is executed. Furthermore, the traditional multiply-add-fused still causes some power consumption in addition unit when only the multiplication is executed. Consequently, we use latches to decrease the dynamic power consumption of the addition units. When executing only the addition operation, we also use latches to decrease the dynamic power consumption of the multiplication unit. Key words: low power, A Variable-precision floating point multiply-add-fused, A Variable-precision function interpolator