A Variable-precision Architecture for Special Function and Floating-point Multiply-add-fused Operation
碩士 === 國立中山大學 === 資訊工程學系研究所 === 103 === This thesis presents a variable-precision floating-point arithmetic unit based on IEEE-754 single precision floating standard. This arithmetic unit combines special function interpolator and floating-point multiply-add-fused. The arithmetic unit provides Expon...
| Main Authors: | , |
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| Format: | Others |
| Language: | zh-TW |
| Published: |
2015
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| Online Access: | http://ndltd.ncl.edu.tw/handle/9u4ku9 |