| Summary: | 碩士 === 國立中山大學 === 資訊工程學系研究所 === 103 === In this thesis, a 10-bit binary search assisted time-interleaved SAR ADC operating in 250Ms/s sampling rate with 1.2 supply voltage is presented. The ADC adopt TSMC 90nm process and can be used for receiving in front-end chip of wireless communication system.
In circuit design, we take BS-ADC and SAR-ADC’s advantage for the requirement of high sampling rate and low power consumption and separate ADC in two stages. The first stage is Binary-search ADC which converts high five bit at 250Ms/s sampling rate. Due to additional switching circuit to select correct reference voltage, the need of comparators in BS-ADC can be substantially reduced. The second stage is two-channel SAR ADCs which convert low five bit. Each channel operates at 125Ms/s. In binary-weight capacitor array, we give half-reference voltage for LSB capacitor switching with monotonic switching method. Compared to conventional binary-weight capacitor array, the proposed architecture can reduce total capacitance by 75%. The entire architecture is designed in fully-differential circuit to reduce common mode noise and improve the linearity of the circuit.
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