A High-Speed Two-Step Binary-Search Assisted Time-Interleaved SAR ADC
碩士 === 國立中山大學 === 資訊工程學系研究所 === 103 === In this thesis, a 10-bit binary search assisted time-interleaved SAR ADC operating in 250Ms/s sampling rate with 1.2 supply voltage is presented. The ADC adopt TSMC 90nm process and can be used for receiving in front-end chip of wireless communication system....
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2015
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| Online Access: | http://ndltd.ncl.edu.tw/handle/n6jsr8 |