A Study of Strain Effects on the Novel GAA Raised Source / Drain Sub-10nm Poly-Si NW Channel TFTs with Self-Aligned Corked Gate Structure

• Main Authors: Teng, Yung-Ching, 鄧永旌
• Other Authors: Chao, Tien-Sheng
• Format: Others
• Language: zh-TW
• Published: 2014
• Online Access: http://ndltd.ncl.edu.tw/handle/05019387566102117069

碩士 === 國立交通大學 === 理學院應用科技學程 === 103 === Recently, due to aggressive scaling of device structures in MOSFETs technology, the performance of MOSFETs has become a huge challenge in ultra large scale integrated (ULSI) fabrication. The control of short channel effect (SCE) becomes crucial owing to the shrinking of gate length. Therefore, the seeking of novel structures to replace traditional planar MOSFETs is essential for the next generation technology node. Because of the significant short channel effect, the excellent gate control ability of device plays an important role in the gate length on the order of atomic dimensions. The multiple-gate architectures have electrostatic advantages over traditional planar devices. The additional dimensions of the gate provide better gate control ability, and therefore reduce the short channel effect. Consequently, GAA (Gate-All-Around) nanowire transistors are the most promising advanced architecture candidates for the next generation technology node. In recent years, there has been considerable attention from numerous consumer electronics manufacturers to apply flexible display in electronic paper, mobile phones and other consumer electronics. Because the demand for flexible consumer electronics is increasing, flexible peripheral circuits are needed. However, the impacts of mechanical stress on extremely small scale device, such as sub-10-nm GAA nanowire FETs has been rarely addressed in the previous reports. In this thesis, we describe a study of characteristics of drain current and threshold voltage of sub-10-nm GAA nanowire FETs under externally applied mechanical stress.