| Summary: | 博士 === 國立交通大學 === 電控工程研究所 === 103 === 3D ICs are considered as one of the emerging techniques for implementing the next-generation ICs. 3D IC techniques such as through-silicon via (TSV) provide vertical and shorter connections for inter-die communication. Thus, the 3D IC achieves many advantages
such as decreased power, reduced signal latency and higher performance. However, the 3D structure leads to new test challenges. The main issues of testing 3D ICs are the reduced controllability and observability due to the lack of accessible I/O pads. From this point of view, the circuits under test incorporated with some on-chip design-for-testability (DFT) or
built-in self-test (BIST) functions are highly demanded for 3D ICs.
In this dissertation, we propose two fully integrated BIST designs to test the signal-to-noise-and-distortion ratio (SNDR), dynamic range, frequency response, gain error, and offset of Delta-Sigma ADCs. The Delta-Sigma ADC under test (AUT) adopts the de-correlating
design-for-digital-testability (D3T) scheme to implement the input stage. The D3T scheme can convert a pulse-density-modulated (PDM) bit-stream into the required high-quality analog stimulus. In this way, the design effort of the high-precision analog stimulus generator is greatly eased. The first BIST design uses the modified controlled sine wave fitting (MCSWF) method. Benefiting from its real-time simple computations, the MCSWF BIST design needs neither bulk memory to store the analyzed samples nor a costly CPU/DSP. The hardware
overhead of the all-digital BIST circuit design is only 9.9 gates. The fully integrated BIST Delta-Sigma ADC has been fabricated in a 0.18-um CMOS process and was tested on the HOY wireless test platform to exhibit the possibility of wirelessly testing analog and mixed-signal (AMS) circuits. Experimental results show that the MCSWF BIST design achieves a test bandwidth of 16 kHz which is very close to the rated 20-kHz bandwidth of the Delta-Sigma AUT.
To address the test bandwidth limitation, we propose the in-phase and quadrature waves fitting (IQWF) method which retains the real-time computation feature. The second fully integrated BIST Delta-Sigma ADC has been fabricated in a 0.18-um CMOS process. Measurement results show that the IQWF BIST design successfully achieves a test bandwidth as wide as the rated 20-kHz bandwidth of the Delta-Sigma AUT.
The proposed BIST designs eliminate the need of AMS ATE without compromising test quality, and thus greatly reduce the test cost. Most importantly, they provide test solutions for the applications in which conventional test resources are not available such as 3D ICs.
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