An All Digital Phase-Locked Loop Using Multi-Stage TDC with 1ps Minimum Resolution
碩士 === 國立交通大學 === 電機工程學系 === 103 === With the rapid growth of technology and the trend of integrated circuits, the Phase-Locked Loop (PLL) plays an important role in a variety of integrated circuit applications. The Phase-Locked Loop generates a stable clock signal as a reference signal to ensure ci...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2014
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| Online Access: | http://ndltd.ncl.edu.tw/handle/37euwp |