| Summary: | 博士 === 國立交通大學 === 電子工程學系 電子研究所 === 103 === In this thesis, novel schemes using low-temperature wafer bonding technology for memory stacking and CMOS imager sensor (CIS) module applications are developed and investigated. One is low-temperature micro-bump and adhesive hybrid wafer bonding with fine pitch interconnect for memory stacking. The other is novel scheme with low-temperature adhesive bonding combination with temporary bonding/de-bonding technique for CIS wafer-level packaging (WLP). The low-temperature wafer bonding technologies are targeted to be less than 250 °C, which decreases the induced thermo-stress and possible damages, and satisfies low thermal budget requirement on most devices.
A wafer-level 3D integration scheme with Cu TSVs based on micro-bump and adhesive hybrid bonding is developed to provide a simplified flow, low temperature, and highly reliable solution for memory stacking. Herein Cu/Sn micro-bump and polymer adhesive are adopted for low temperature hybrid bonding to achieve intrinsic interconnect with adhesive sealing around. This scheme also enhances the reliability of the stacked devices and serving as reinforcement of the mechanical stability to withstand the severe wafer thinning and backside processes. Firstly, several popular passivation materials are evaluated as the hybrid bonding adhesive. The bonding integrity and hybrid compatibility with metal of these materials are investigated and assessed. Some key factors for hybrid bonding are studied, and the conditions of Cu/Sn and qualified adhesive hybrid bonding are optimized to enhance the bonding performance. With precise control of metal/adhesive thickness and clean metal surface, the hybrid scheme of Cu/Sn bump and patterned Benzocyclobutene (BCB) adhesive is qualified and can be adopted to perform 3D integration.
Accordingly, a wafer-level 3D integration scheme with Cu TSVs based on Cu/Sn micro-bump and BCB adhesive hybrid bonding is further developed and demonstrated. TEG wafer with different TSV/bump sizes and pitches are designed with daisy chain, Kelvin structure, and TSV leakage test patterns for investigation and characterization. Key technologies, including TSV fabrication, micro-bumping, hybrid scheme formation, hybrid bonding, wafer thinning, and backside RDL formation are developed and integrated to perform the 3D integration scheme. 40-µm thickness wafers with 5 µm TSVs, 10 µm micro-bumps with 20 µm pitch, using 250 °C low temperature W2W hybrid bonding are successfully integrated in the 3D integration platform.
Following the successful development of the wafer-level 3D integration scheme with Cu TSVs based on Cu/Sn micro-bump and BCB adhesive hybrid bonding, daisy chain feature and Kelvin structure with 5 μm and 10 μm TSV in the scheme are fabricated and investigated with electrical characterization and reliability assessment. TSV pair with test pattern is designed for the leakage investigation. The characteristics of micro-joint, single Cu TSV, and Cu/Sn micro-joint interconnect, and bond chain structure with a series of Cu TSVs and Cu/Sn micro-joints interconnect are investigated with excellent performance, and the scheme can pass multiple AC current stressing, humidity test, and TCT reliability assessment. The characterization and reliability assessment results indicate that the 3D integration scheme possesses excellent electrical performance and reliability, and could be extensively applied for 3D product applications.
In addition, another novel scheme with low-temperature adhesive bonding combination by utilizing temporary bonding/de-bonding technique for backside illuminated (BSI) CIS wafer-level packaging is investigated and developed. TEG wafer is designed first to evaluate and integrate the novel BSI-CIS structure and process, where no carrier wafer is required and the complex fusion bonding and TSV fabrication processes can be skipped accordingly. The characteristics and reliability of the scheme are investigated, results show excellent integration integrity and reliability. Real device wafer is then designed for further verification and demonstration with functional test. Stacking of BSI-CIS and analog-to-digital converter (ADC) real device is demonstrated. The image function is successfully verified with good quality, which indicates the excellent performance as well. This scheme provides a realizable low cost solution for the next generation CIS and further 3D integrated imager applications.
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