| Summary: | 碩士 === 國立交通大學 === 電子工程學系 電子研究所 === 103 === As the modern ICs are facing increasingly tougher DPPM requirements, and the insufficient of the traditional fault model in testing intra-cell defects, new testing techniques such as Gate-Exhaustive, N-Detect, or Cell-aware were proposed. Though the fault coverage can be improved by these methods, the pattern count, which is the main cost of testing, would be significantly in- creased. In this thesis, a defect aware testing flow for industrial design is presented. The Flow, can target the actual root cause of intra-cell defects while not adding too much patterns and could increase the defect coverage. The rear half of the flow is the proposed methodology which can be applied independently to the state-of-the-art commercial tool to reduce the generated patterns. The newly proposed pattern reduction methodology and the cell- aware testing flow have been evaluated with tsmc 65nm technology on 845 library cells and both ISCAS and real industrial design with up to 1.8 mil- lion defects. The experiment result shows an average reduction of 70% in the pattern count without sacrificing the defect coverage.
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