| Summary: | 碩士 === 國立交通大學 === 電子工程學系 電子研究所 === 103 === This thesis investigates and analyses the variability of metal-gate work function variation (WFV) and fin line-edge-roughness (fin LER) on the homojunction TFET and FinFET devices and logic circuits operating in near-threshold region by using 3D atomistic Technology Computer Aided Design (TCAD) mixed-mode Monte-Carlo simulation and look-up table based Verilog-A model HSPICE simulation. It contains two topics and is organized as follows.
In the first part, we compare the impacts on TFET and FinFET device Vt, S.S.ave, Ion, Ioff and Cg,ave considering WFV and fin LER. Simulation results show that the variation sources have different impacts on TFET and FinFET devices due to the different mechanism between them. This is apparent for the cases considering WFV, that the variability of Ion and Ioff are comparable with the almost equal S.S. for FinFET, in contrast, the variability of Ion is smaller while that of Ioff is more significant for TFET due to their different dependence on the WFV patterns. In addition, the band diagram dispersion caused by WFV leads to larger Ioff distribution. The Cg,ave variation of both TFET and FinFET considering fin LER is worse than that with WFV.
In the second part, we present a comparative analysis for TFET and FinFET on carry-look-ahead adder delay, PDP and leakage power considering WFV and fin LER. The simulation results are related to the variability of Ion, Ioff and Cg,ave in the first part. As the operating voltage is reducing (under ~0.3V), the delay and PDP of TFET are much better than FinFET even with the impact of random variation. However, the leakage power variability of TFET is worse than FinFET due to the worse Ioff variability and the larger Ioff trend of TFET devices.
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