Chip Implementation of Power-Efficient Multimode LDPC Decoder with Early Termination

碩士 === 國立中興大學 === 電機工程學系所 === 103 === VLSI circuit design and implementation of multi-mode low density parity check (LDPC) decoders for communication systems is proposed in this thesis. The purposes of design architecture are reducing chip area and increasing throughput. To reduce the number of iter...

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Bibliographic Details
Main Authors: Yung-Hao Chou, 周雍皓
Other Authors: 林泓均
Format: Others
Language:zh-TW
Published: 2015
Online Access:http://ndltd.ncl.edu.tw/handle/85216871827850256807
Description
Summary:碩士 === 國立中興大學 === 電機工程學系所 === 103 === VLSI circuit design and implementation of multi-mode low density parity check (LDPC) decoders for communication systems is proposed in this thesis. The purposes of design architecture are reducing chip area and increasing throughput. To reduce the number of iterations, early termination mechanism is included to futher reduce power consumption and enhance throughput. The porposed decoder supports four coding rates (CR), namely, Mode 1 (CR = 1/2), Mode 2 (CR = 3/4), Mode 3 (CR = 5/6), and Mode 4(CR = 7/8). The CR can be selected according to different channel environments. After optimization of the structure of patity check matrix, good decoding abilities of the four coding rates have been verified. With the appropriate pipeline design, the dual path architectures for Mode 2 to Mode 4 and the triple path architecture for Mode 1 achieve 100% hardware utilization rate of core computation units such as check node nuits (CNU). With massive hardware reuse design, the chip area and power consumption are reduced significantly, while throughput is still very high. In addition, some hardware modules in the decoder were analyzed and optimized to further reduce chip area and power consumption. Through the analysis of early termination, syndrome check does not degrade decoding ability and is easy to be implemented for hardware design. The average numbers of iterations are 3.2 at EbNo = 12.5 dB and 2.5 at EbNo = 13 dB. That results in reducing computation time and power consumption additionally. The decoder was designed using TSMC 90nm CMOS technology. The core area is 1.54mm2 and the total chip area is 3.48mm2. The troughput is up to 6.4Gbps and power consumption is 138mW with iteration number of 5 at clock frequency of 200MHz. For the enhanced version, the clock frequency can be increased to 300MHz, so the throughput can reach 9.6Gbps with power consumption of 214mW. The proposed architecture comsumes the least power per unit of throughput with the throughput close to 10Gbps in comparision with the other literature.