Chip Implementation of Power-Efficient Multimode LDPC Decoder with Early Termination
碩士 === 國立中興大學 === 電機工程學系所 === 103 === VLSI circuit design and implementation of multi-mode low density parity check (LDPC) decoders for communication systems is proposed in this thesis. The purposes of design architecture are reducing chip area and increasing throughput. To reduce the number of iter...
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| Format: | Others |
| Language: | zh-TW |
| Published: |
2015
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| Online Access: | http://ndltd.ncl.edu.tw/handle/85216871827850256807 |