Design of 5 Gb/s Pseudo-Random Bit Sequence Generator and Checker Circuits Using MOS Current Mode Logic

• Main Authors: Fu-Yun Jiang, 江福運
• Other Authors: Jau-Ji Jou
• Format: Others
• Language: zh-TW
• Published: 2015
• Online Access: http://ndltd.ncl.edu.tw/handle/65978203555915368019

碩士 === 國立高雄應用科技大學 === 電子工程系碩士班 === 103 === In this thesis, two pseudo-random bit sequence (PRBS) generators with selectable sequence length and a PRBS checker were designed in TSMC 0.18μm complementary metal-oxide-semiconductor (CMOS) process. Using a 2×1 selector to choose the feedback path, the PRBS generators can generate the PRBS signal with different sequence length. Using current-mode logic (CML) D-type flip-flop (DFF), the PRBS generators can be operated at higher rate. The sequence length of the first PRBS generator can select 27-1 or 210-1, the circuit can be operated at 5 Gb/s, the power dissipation of the chip is 77.4 mW, and its area is 0.55×0.51mm2. For the second PRBS generator, the 27-1 and 215-1 sequence lengths can be selected, its operation rate can be at 6 Gb/s, its power consumption is 90.2mW, and its area is 0.51×0.6 mm2. The PRBS checker which can accurately show error bits and the PRBS generator which can add error bits are designed. The PRBS checker and generator circuits are integrated in a chip for bit error measurement. The chip can be applied in bit error testing for 27-1 sequence length, its operation rate is at 5 Gb/s, its total power consumption is 202.2mW, and its area is 1.06×0.9 mm2.