Design of 5 Gb/s Pseudo-Random Bit Sequence Generator and Checker Circuits Using MOS Current Mode Logic
碩士 === 國立高雄應用科技大學 === 電子工程系碩士班 === 103 === In this thesis, two pseudo-random bit sequence (PRBS) generators with selectable sequence length and a PRBS checker were designed in TSMC 0.18μm complementary metal-oxide-semiconductor (CMOS) process. Using a 2×1 selector to choose the feedback path, the PR...
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| Format: | Others |
| Language: | zh-TW |
| Published: |
2015
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| Online Access: | http://ndltd.ncl.edu.tw/handle/65978203555915368019 |