Hardware-Efficient Triple-Modular-Redundancy Soft-Error-Tolerant Arithmetic Circuit Architecture Design

Hardware-Efficient Triple-Modular-Redundancy Soft-Error-Tolerant Arithmetic Circuit Architecture Design

碩士 === 長庚大學 === 電機工程學系 === 103

Bibliographic Details
Main Authors:	Pin Hsi Lin, 林品希
Other Authors:	I. C. Wey
Format:	Others
Published:	2015
Online Access:	http://ndltd.ncl.edu.tw/handle/4ta3yt

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