Parasitic-aware Common-centroid Binary-weighted Capacitor Layout Generation with Integrated Sizing, Placement, Routing and Shielding Techniques
碩士 === 國立中正大學 === 電機工程研究所 === 103 === Capacitor sizing is a crucial step when designing a charge-scaling digital-to-analog converter. Larger capacitor size can achieve better circuit accuracy and performance due to less impact from random, systematic, and parasitic mismatch. However, it also results...
| Main Authors: | , |
|---|---|
| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2015
|
| Online Access: | http://ndltd.ncl.edu.tw/handle/pqnzpc |
| Summary: | 碩士 === 國立中正大學 === 電機工程研究所 === 103 === Capacitor sizing is a crucial step when designing a charge-scaling digital-to-analog converter. Larger capacitor size can achieve better circuit accuracy and performance due to less impact from random, systematic, and parasitic mismatch. However, it also results in a larger chip area and even more power consumption. In addition to minimizing random and systematic mismatch during common-centroid capacitor placement, [Lin et. al., DAC’14][1] presents the first problem formulation in the literature which simultaneously considers capacitor sizing and parasitic matching during common-centroid capacitor layout generation such that the power consumption is minimized while the circuit accuracy/performance is also satisfied. Based on the problem formulation and approach, we present the shielding technique to improve the [1]'s approach. The experimental result shows our approach can achieve a smaller chip area and lower power reduction compared with the state of the art.
|
|---|