Parasitic-aware Common-centroid Binary-weighted Capacitor Layout Generation with Integrated Sizing, Placement, Routing and Shielding Techniques
碩士 === 國立中正大學 === 電機工程研究所 === 103 === Capacitor sizing is a crucial step when designing a charge-scaling digital-to-analog converter. Larger capacitor size can achieve better circuit accuracy and performance due to less impact from random, systematic, and parasitic mismatch. However, it also results...
| Main Authors: | , |
|---|---|
| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2015
|
| Online Access: | http://ndltd.ncl.edu.tw/handle/pqnzpc |