A Study of ESD Robustness in the HV-nLDMOS with Super-Junction structures

• Main Authors: Yi-Sheng Lai, 賴義勝
• Other Authors: Shen-Li Chen
• Format: Others
• Language: zh-TW
• Published: 2014
• Online Access: http://ndltd.ncl.edu.tw/handle/98550470378928087522

碩士 === 國立聯合大學 === 電子工程學系碩士班 === 102 === Due to process technology is advancing with each passing day, device feature size miniature and power devices grown up rapidly, then the electrostatic discharge (ESD) problem becomes more serious. And, today’s driver IC, automotive electronics and power electronics applications usually are operated at high voltage conditions, so that they need to withstand a high voltage or high current situation. Therefore, how to provide a better quality and reliability in the HV BCD process are very important. This thesis consists of five chapters, the Chapter 1 is the motivation, which explains the related applications of high voltage power devices; the Chapter 2 is principles of ESD-related, which introduces the a theory, device structures in this work, and the TLP measurement system; IC layout designs, including the structure and parameters modulation of all devices are described in the Chapter 3; the Chapter 4 is the measurement results and discussion; finally, the Chapter V is a conclusion. Here, a TSMC 0.25 µm HV BCD process technology is used to design an HV MOSFET of adding an SJ structure, and aim at different SJ structures make a series of parameters modulation. There are four types of SJ structures will be explored, which are parallel SJ-nLDMOS_Type-1, vertical SJ-nLDMOS_Type-2, modulated D value SJ-nLDMOS_Type-3 and unbalanced SJ-nLDMOS_Type-4, respectively. Meanwhile, not only in the nLDMOS, but also pLDMOS devices are realized in this thesis. Furthermore, the parallel SJ-nLDMOS_Type-1 and vertical SJ-nLDMOS_Type-2, which will be embedded with a parasitic pnp SCR structure to evalute whether with a better ESD protection ability or not.