A High Resolution Field Programmable Gate Array Time-to-Digital Converter Based On Delay Wrapping And Phase Sorting

• Main Authors: Wei-Xiang Tsai, 蔡為翔
• Other Authors: Poki Chen
• Format: Others
• Language: zh-TW
• Published: 2014
• Online Access: http://ndltd.ncl.edu.tw/handle/32700484143504810040

碩士 === 國立臺灣科技大學 === 電子工程系 === 102 === A high resolution FPGA time-to-digital converter based on delay wrapping and phase sorting to achieve an extremely fine resolution of 1ps is proposed in this thesis. A single clock passed a series of delay elements is used to generate multiple reference clocks with different delays. Due to periodicity, those delays will be equivalently warpped between 0~360?a and then phase sorting is applied to select proper reference clocks with delays uniformly distributed over 0~360?a based on the required solution to achieve the best linearity. Furthermore, to reduce the impact of temperature-sensitive the offset, a cancellation circuit is created to substantially reduce offset and confine the output difference within 10LSB for the same input interval. With 1ps such a fine resolution, the long-term integral nonlinearity (INL) is measured to be merely -2.09~2.36 LSB and the corresponding differential nonlinearity (DNL) is -1.45~1.73LSB. This TDC was tested to be fully functional over 0?aC to 50?aC ambient temperature range with extremely low resolution variations. Its performance is even much superior than most full-custom design TDCs.