| Summary: | 碩士 === 國立臺灣大學 === 電機工程學研究所 === 102 === High-level synthesis (HLS) compilers usually provide some supported target architectures that can be chosen by users; however, the limited architectures may not fit the requirements of underlying systems. In this paper, we propose a target architecture embedded with a scratchpad memory (SPM) and an SDRAM that allows users to customize their design. The proposed architecture has been integrated with an HLS compiler, called LegUp, so that the synthesizing computation can be executed on the target architecture with the SPM and the SDRAM. In addition, we use a dual port memory controller to enhance the performance of the target architecture. An algorithm based on integer linear programming is used to allocate data to the proposed SPM at compile time. The experiment results show that the proposed architecture can effectively achieve the 23%~43% execution time of an architecture without an SPM, and can solve huge problems by using the external memory.
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