| Summary: | 博士 === 國立臺灣大學 === 電子工程學研究所 === 102 === We demonstrated the self-aligned double layers single crystal silicon nanowires in silicon substrate by the control of the electric field effect of anodic oxidation. The wire pattern was defined by E-beam lithography and was etched by reactive ion etching. The minimum width of single crystal Si nanowire is around 9 nm. The electrical characteristics of non-planar substrate MOS capacitors with ultra thin oxides and different gate areas are also studied and discussed in this work. The capacitance-voltage (C-V) responses of non-planar and planar MOS capacitors are comprehensively studied by comparing their C-V behaviors from depletion to DD regions. The convex corner exhibits broader depletion width (WD) due to the coupling effect. The minority carrier will also be crowded in the non-planar corner and therefore introduce obvious extra low frequency effect in strong inversion region. Moreover, the non-uniform deep depletion (DD) behaviors for non-planar sample and the area dependent DD for planar sample are observed. It is also noticed that the characteristics of interface trap was observed by applying the combined high-low frequency capacitance method. The non-planar MOS exhibits redistribution behaviors of interface trap due to the non-(100) orientation effect. In the planar samples, the major type of interface traps is donor-like. However, both of donor-like and acceptor-like interface traps are existed in non-planar sample as compared with the planar one. After the stress treatment, the non-uniform oxide electric fields in concave and convex corners are responsible for the irregular saturation tunneling current behavior in non-planar samples which is different from planar one. Finally, the non-planar substrate metal-oxide-semiconductor (MOS) photo-capacitance detector with enhanced deep depletion (DD) at convex corner was also demonstrated in this work. It was found that the significant enhanced photo-capacitance variation sensitivity (ΔC/C) of 85.5% was achieved for non-planar MOS device which respect to that of 7% for planar one under the same illumination intensity of 90mW/cm2.
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