Design and Analysis of Tens of Gb/s Multi-Channel Clock and Data Recovery Circuits
碩士 === 國立臺灣大學 === 電子工程學研究所 === 102 === Wireline communication keeps exponential growth in recent years. To increase thethroughput of I/O connection, we can increase the data rata of I/O connection. However, the higher data rate may suffer from more channel loss. This increases the design difficulty...
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| Format: | Others |
| Language: | zh-TW |
| Published: |
2014
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| Online Access: | http://ndltd.ncl.edu.tw/handle/65882805653499707219 |