A Fast Parallel Approach for Common Path Pessimism Removal
碩士 === 國立清華大學 === 資訊工程學系 === 102 === Static timing analysis has always been indispensable in integrated circuit design. In order to consider design and electrical complexities (e.g., crosstalk coupling, voltage drops) as well as manufacturing and environmental variations, timing analysis is typicall...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2014
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| Online Access: | http://ndltd.ncl.edu.tw/handle/90266982150218059640 |