A Wide-Range and Harmonic-Free 10-bit SAR All-Digital Delay-Locked Loop
碩士 === 國立中山大學 === 資訊工程學系研究所 === 102 === This delay locked loop uses TSMC 90nm process. It uses the shift-counting type successive approximation register to control the digital delay line, which can solve the problem of harmonic lock. The part of delay line uses a complementary way to improve the ran...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2014
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| Online Access: | http://ndltd.ncl.edu.tw/handle/y39qh6 |