Design of Timing-Error-Tolerant VLSI Circuits for RSA Encryption and Decryption

• Main Authors: Tsung-Han Wu, 吳宗翰
• Other Authors: Hsin-Chou Chi
• Format: Others
• Published: 2014
• Online Access: http://ndltd.ncl.edu.tw/handle/p868td

碩士 === 國立東華大學 === 電機工程學系 === 102 === As the feature size of chips shrinks with semiconductor technology advancing, the size of transistors and their operating voltage keep decreasing. One of the major problems with advanced semiconductor technology is timing errors caused by process variation and device aging. With such problems, conventional worst-case designs suffer poor system performance. This thesis proposes an aggressive design technique for VLSI circuits for RSA encryption and decryption for tolerating timing errors. We have developed a methodology of designing reconfigurable VLSI circuits for RSA encryption and decryption that can tolerate timing errors. The reconfigurable VLSI circuits for RSA encryption and decryption are resilient to any timing errors occurring at any stage and any time. When the timing error occurs, the system reconfigures the buffer cells of VLSI circuits for RSA encryption and decryption with little performance degradation. We have applied our technique to the VLSI circuits for RSA encryption and decryption designs. The implementation results show that our proposed designs achieve tolerance of timing errors with reasonable cost.