Supply Sensitivity Compensation Scheme of a 0.5V ALL-Digital Phase-Locked Loop
碩士 === 國立交通大學 === 電機工程學系 === 102 === This thesis proposes a supply sensitivity compensation scheme for a 0.5V all-digital phase-locked loop. This design includes an ADPLL, a 4-bit adjustable compensation circuit, and a digital detect circuit. The compensation scheme is designed for foreground execut...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2014
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| Online Access: | http://ndltd.ncl.edu.tw/handle/zf7ecr |