A Temperature-Aware Statistical Soft-Error-Rate Analysis Framework for Combinational Circuits
碩士 === 國立交通大學 === 電信工程研究所 === 102 === Soft error has become one of the most critical reliability issues for nano-scaled CMOS designs. Many previous works discovered that the pulse width due to a particle strike on the device increases with temperature, but its chip-level effect has not yet been inve...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2013
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| Online Access: | http://ndltd.ncl.edu.tw/handle/73480984944131035265 |