Design of Multi-Stage Computing Engine for DSP Applications
碩士 === 國立交通大學 === 電子工程學系 電子研究所 === 102 === In the history of processor development, we observe that Reduced Instruction Set Computer (RISC) processors have already become mainstream for several years. It has a simple and regular datapath and thus facilitates pipelining for high performance. But its...
| Main Authors: | , |
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| Format: | Others |
| Language: | en_US |
| Published: |
2014
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| Online Access: | http://ndltd.ncl.edu.tw/handle/je3ust |