Fabrication and Analysis of Novel Poly-Si Nanowire Non-Volatile Memory Devices

• Main Authors: Lee, Ko-Hui, 李克慧
• Other Authors: Lin, Horng-Chih
• Format: Others
• Language: en_US
• Published: 2014
• Online Access: http://ndltd.ncl.edu.tw/handle/56246598329572707973

博士 === 國立交通大學 === 電子工程學系 電子研究所 === 102 === In this dissertation, simple and low-cost self-aligned processes are proposed to fabricate high-performance polycrystalline silicon (poly-Si) nanowire (NW) field-effect transistors (FETs) and non-volatile memory (NVM) devices. Poly-Si NW devices with sub-lithographic channel length are successfully fabricated by “side-wall spacer technique” and “lateral etching technique” using only i-line based photolithography tool. Furthermore, both rectangular- and triangular-shaped NW devices are fabricated with fine-tuning process conditions. To investigate the influence of the channel size and shape of NW SONOS devices on memory characteristics, different channel sizes of rectangular- or triangular shaped gate-all-around (GAA) poly-Si NW SONOS memory devices are compared and analyzed. From the experimental results, it is observed that, owing to the enhancement of electric field around the sharp corners and larger band bending across the tunnel oxide, the triangular-shaped poly-Si NW devices show obviously higher programming/erasing (P/E) efficiency than that of the rectangular-shaped poly-Si NW devices. Also, as compared with NW devices with different channel size, the smaller NW channel devices show better endurance characteristics, and it is related to the more uniform stored electron distribution in the nitride CT-layer around the whole NW channel. On the development of high-performance poly-Si NVM devices, we have proposed a triangular-shaped poly-Si NW floating-gate (FG) memory device to overcome the conventional NOR-type memory scaling bottleneck. A GAA triangular-shaped NW channel configuration is intentionally adopted to increase the electric field of corner regions. Due to the electron redistribution properties of n+ poly-Si FG, extremely high and unsaturated P/E speed under low operation voltage is successfully demonstrated because the FG charge storage layer allows continuous electrons injection from the high electric field corner regions during programming. On the other hand, in order to further improve the performance of poly-Si NW charge trapping (CT)-type memory devices, two kinds of bandgap-engineered CT-layers are developed, one is silicon nanocrystals (Si-NCs) embedded in the nitride layer, and the other is bandgap-engineered HfAlO (BE-HfAlO) CT-layer. For the former CT-layer, we have fabricated poly-Si NW SONOS memory devices embedded with zero, single, and double Si-NCs layers in the CT nitride. NW memory devices with double Si-NCs layers exhibit slower P/E speed but larger memory window and longer retention time than those of conventional SONOS NW devices. For the second bandgap engineering work, we have designed a high performance device with BE-HfAlO CT layer. With gradually varying Al/Hf ratio in HfAlO film, the benefits of BE-HfAlO CT-layer come from the increased charge-trapping probability due to the smaller bandgap and shallower trapping level near the tunnel oxide, and the decreased charge loss probability due to the larger bandgap and deeper trapping level near the blocking oxide, therefore, the BE-HfAlO devices show high P/E speed, which is comparable to HfO2 CT-layer memory devices. Also, excellent retention and endurance characteristics are shown in BE-HfAlO devices due to the increase of the recrystallization temperature of Hf-based film incorporated with Al atom and elimination of the generation of grain boundaries in CT-layer. Finally, a high-performance short-channel tri-gated poly-Si NW FET is developed by using simple sidewall spacer and lateral etching techniques without employing costly lithographic tools. Devices with channel length of 120 nm and NW thickness of 25 nm are successfully formed by the self-aligned process. The devices exhibit superior electrical characteristics due to the strong gate controllability, i.e., S.S. of 102 mV/dec, DIBL of 74.4 mV/V, and extremely high ION/IOFF ratio of 4.4 × 108. This flexible approach is feasible for fabricating test devices for probing the nano-scale phenomena and manufacturing of the future 3-D stackable devices/circuits.