| Summary: | 碩士 === 國立交通大學 === 電子工程學系 電子研究所 === 102 === Static timing analysis is a key process to guarantee timing closure for modern IC designs. Nevertheless, fast growing design complexities and increasing on-chip variations complicate this process. To capture more accurate timing performance of a design, common path pessimism removal is prevalent to eliminate artificially induced pessimism in clock paths during timing analysis.
To avoid exhaustive exploration on all paths in a design, in this thesis, we present a novel timing analysis framework removing common path pessimism based on block-based static timing analysis, timing graph reduction, dynamic bounding, and parallel computing. We further introduce three practical extensions that are half-cycle paths, multi-cycle paths and clock reconvergence. Experimental results show that the proposed method is highly scalable, especially with short runtimes for large-scale designs. Moreover, our approach outperforms TAU 2014 timing contest winners, generating accurate results and achieving more than 2.13X speedups.
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