Timing Analysis with Common Path Pessimism Removal via Dynamic Bounding and Cell Merging
碩士 === 國立交通大學 === 電子工程學系 電子研究所 === 102 === Static timing analysis is a key process to guarantee timing closure for modern IC designs. Nevertheless, fast growing design complexities and increasing on-chip variations complicate this process. To capture more accurate timing performance of a design, com...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2014
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| Online Access: | http://ndltd.ncl.edu.tw/handle/s5e4t9 |