| Summary: | 碩士 === 國立交通大學 === 電子工程學系 電子研究所 === 102 === In the conventional NAND flash memory system, BCH code has been widely used due to its simplicity in hardware implementation when hard input is adopted. However, as the shrinking of manufacturing process and the increasing number of bits stored per flash memory cell, the raw bit error rate keeps worsening and the BCH code becomes insufficient for providing enough error correcting capacity. In this thesis, 2-bit and 3-bit soft input LDPC decoders are presented to outperform BCH code under the similar code rate, and efficiently prolong the endurance of TLC NAND flash memory.
The proposed (9168,8217) LDPC code is constructed from the Separable Circulant-Based LDPC code algorithm. By further adopting the Cycle-Consistency Matrix technique, our LDPC code reduces the number of absorbing sets, and hence lowers the error floor effect. There is no error floor observed before frame error rate (FER) around 10-9. Moreover, concepts of mutual information and simulated annealing are adopted in searching for optimum quantization of channel value in order to provide more accurate input information of LDPC codes. Using distribution data extracted from real TLC NAND flash memory, the simulation of LDPC decoder has been demonstrated and proved that in our approach, the lifetime of TLC NAND flash memory is at least doubled compared with BCH code having the same code rate.
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