Topology similarity driven floorplan algorithm for wirelength minimization
碩士 === 國立交通大學 === 電子工程學系 電子研究所 === 102 === Floorplanning is in the early stages of VLSI physical design. It determines the locations of modules and significantly governs the chip dimensions and the total wirelength on the chip. Thus it is important in terms of both fabrication cost and chip performa...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2013
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| Online Access: | http://ndltd.ncl.edu.tw/handle/02150322207536554292 |