Using High-K Dielectric/Metal Gate with theChemical Oxide Integration Scheme to AchieveHigh Performance 20-nm n/pMOS Devices
博士 === 國立成功大學 === 微電子工程研究所 === 102 === In order to achieve the purpose of high performance metal-oxide-semiconductor (MOS) devices of 20-nm technology node, the dielectric material and gate length of MOS devices are must continuously thinning and scaling down. However, the gate leakage current den...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2014
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| Online Access: | http://ndltd.ncl.edu.tw/handle/58844834237986740731 |