Discussion of the Failure at the Conducting Layer for Direct Chip Attach Package
碩士 === 國立成功大學 === 工程科學系 === 102 === In recent years, with the continuous progress and innovation of the electronic products progress, the requirements for frivolous short, high frequency, high speed and the high heat emission to the IC chip has increased. As a result, the flip chip and some similar...
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ndltd-TW-102NCKU50280342016-03-07T04:10:56Z http://ndltd.ncl.edu.tw/handle/47329231332951484870 Discussion of the Failure at the Conducting Layer for Direct Chip Attach Package 探討直接晶片接合封裝體在導電層處之破壞分析 Po-YuanHsiao 蕭博元 碩士 國立成功大學 工程科學系 102 In recent years, with the continuous progress and innovation of the electronic products progress, the requirements for frivolous short, high frequency, high speed and the high heat emission to the IC chip has increased. As a result, the flip chip and some similar packages which are facilitated to reduce the IC area become the mainstream product in the market. By adopting the Direct Chip Attach Package, this paper aims to investigate the stress condition at the conducting layer of the package so as to figure out the fragile location of the conducting layer and ensure the stability of product quality. The ANSYS 12.0 finite element analysis is employed as well as the Direct Chip Attach Package is subjected by the thermal cycle of -45℃~125℃. The solder ball is considered as elasticplastic while other components are treated as elastic. The Global/Local Method is adopted for analysis. The material properties of the conducting layer is replaced by equivalent parameters in the global model and the original parameters are restored to each conducting layer in the local model so as to achieve certain accuracy and convergence, and then the stress behaviors of the conducting layer are investigated. It is found that the maximum Y component of stress is -231.06Mpa located at the bottom of oxide layer in high temperature while the maximum Y component of stress is -371.448Mpa located at the top of the copper layer in low temperature. It seems that the two locations are easy to delaminate and crack. The above model is regarded as the standard model. Secondly, the temperature cycle loading, such as high temperature, low temperature, time of constant temperature and the heat rate, is changed to compare with the standard model in which the stress changing and the failure mode in the conducting layer are observed. Finally, the structure of the conducting layer is changed, such as the increase of the amount of copper layers, to analyze its difference from the standard model. By comparing with those factors, the amount of copper layers is more significant factor which is changed from 4 copper layers to the 8 copper layers for the structure of the conducting layer, it shows that more copper layers in conducting layers, higher Y component of stress happening in each part of conducting layers in low temperature. Y component of stress is 31.7% increasing in copper layers and 23.3% increasing in oxide layers. It also shows the opposite results in high temperature where Y component of stress is 102% decreasing in copper layers and 128% decreasing in oxide layers. Rong-Sheng Chen 陳榮盛 2014 學位論文 ; thesis 175 zh-TW |
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碩士 === 國立成功大學 === 工程科學系 === 102 === In recent years, with the continuous progress and innovation of the electronic products progress, the requirements for frivolous short, high frequency, high speed and the high heat emission to the IC chip has increased. As a result, the flip chip and some similar packages which are facilitated to reduce the IC area become the mainstream product in the market. By adopting the Direct Chip Attach Package, this paper aims to investigate the stress condition at the conducting layer of the package so as to figure out the fragile location of the conducting layer and ensure the stability of product quality.
The ANSYS 12.0 finite element analysis is employed as well as the Direct Chip Attach Package is subjected by the thermal cycle of -45℃~125℃. The solder ball is considered as elasticplastic while other components are treated as elastic. The Global/Local Method is adopted for analysis. The material properties of the conducting layer is replaced by equivalent parameters in the global model and the original parameters are restored to each conducting layer in the local model so as to achieve certain accuracy and convergence, and then the stress behaviors of the conducting layer are investigated. It is found that the maximum Y component of stress is -231.06Mpa located at the bottom of oxide layer in high temperature while the maximum Y component of stress is -371.448Mpa located at the top of the copper layer in low temperature. It seems that the two locations are easy to delaminate and crack. The above model is regarded as the standard model.
Secondly, the temperature cycle loading, such as high temperature, low temperature, time of constant temperature and the heat rate, is changed to compare with the standard model in which the stress changing and the failure mode in the conducting layer are observed. Finally, the structure of the conducting layer is changed, such as the increase of the amount of copper layers, to analyze its difference from the standard model. By comparing with those factors, the amount of copper layers is more significant factor which is changed from 4 copper layers to the 8 copper layers for the structure of the conducting layer, it shows that more copper layers in conducting layers, higher Y component of stress happening in each part of conducting layers in low temperature. Y component of stress is 31.7% increasing in copper layers and 23.3% increasing in oxide layers. It also shows the opposite results in high temperature where Y component of stress is 102% decreasing in copper layers and 128% decreasing in oxide layers.
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author2 |
Rong-Sheng Chen |
author_facet |
Rong-Sheng Chen Po-YuanHsiao 蕭博元 |
author |
Po-YuanHsiao 蕭博元 |
spellingShingle |
Po-YuanHsiao 蕭博元 Discussion of the Failure at the Conducting Layer for Direct Chip Attach Package |
author_sort |
Po-YuanHsiao |
title |
Discussion of the Failure at the Conducting Layer for Direct Chip Attach Package |
title_short |
Discussion of the Failure at the Conducting Layer for Direct Chip Attach Package |
title_full |
Discussion of the Failure at the Conducting Layer for Direct Chip Attach Package |
title_fullStr |
Discussion of the Failure at the Conducting Layer for Direct Chip Attach Package |
title_full_unstemmed |
Discussion of the Failure at the Conducting Layer for Direct Chip Attach Package |
title_sort |
discussion of the failure at the conducting layer for direct chip attach package |
publishDate |
2014 |
url |
http://ndltd.ncl.edu.tw/handle/47329231332951484870 |
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