| Summary: | 碩士 === 明新科技大學 === 電子工程研究所 === 102 === With the advancement of technology, the feature size of field-effect transistors coming from semiconductor manufacturing process technology has evolved from sub-micron to 28nm process generation or beyond. Following the Moore’s law, besides the reduction of process cost and the increase of device density in IC due to the dimensional shrinkage of transistor devices, the increase of transistor switch speed is chiefly considered. Promoting until 32-nm node, some semiconductor companies applied the high-K material replacing the SiO2 as gate dielectric. But, the characteristics of high-K material are influenced easily by deposited temperature, especially at the high temperature status. In other words, the crystallization effect for pure high-K material will be obviously observed at the high temperature and easily cause higher gate leakage. Therefore, the amorphous gate dielectric in the advanced process is more impressive due to the device concern.
Although high-K materials propose several benefits, there is oxygen vacancy to difficultly control the threshold voltage (VT) of a transistor and easily degrade the integrity of gate dielectric. The quality of interface state between gate dielectric and channel surface is a latent issue. Therefore, if these drawbacks using some nitridation process to repair the vacancy after high-K deposition is acceptable. There are two feasible nitridation processes: decoupled-plasma nitridation (DPN) and post deposition annealing (PDA).
In this project, gate high-k material used to 28nm devices for basis and gate dielectric with a profile of HfOx/ZrOy/HfOz (HZH) was deposited. Then, the decoupled plasma nitridation (DPN) process or post deposition annealing (PDA) was employed to HZH annealing. The annealing temperature and the nitrogen concentration contributed to electrical characteristics of HK/MG pMOSFETs probed by Early effect was investigated. Through this study, some of device models compared with the traditional must be modified to increase the design window for IC designers.
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