ESD Test and Simulation Analysis with Protection Techniques for IC on board

• Main Authors: Yi-Chen Chou, 周易澄
• Other Authors: 林漢年
• Format: Others
• Language: zh-TW
• Published: 2014
• Online Access: http://ndltd.ncl.edu.tw/handle/41086123635446035927

碩士 === 逢甲大學 === 通訊工程學系 === 102 === In recent years, the integrated circuit (IC) is development, production process quick size evolution, elements reduced to deep submicron stage to promote integrated circuit (IC) performance and computing speed, making ESD (Electrostatic Discharge) protection capabilities are becoming increasingly important, electrostatic discharge protection circuit (ESD protection circuits) on the integrated circuit is designed to make ESD protection purposes, make integrated circuits (IC) at the time when the damage suffered momentary large current can be Input to ESD protection circuit between VSS and VDD and VSS to bypass ESD current. In this paper, the use of international standards IEC 61000-4-2: Electrostatic discharge (ESD), in the printed circuit board, so that when the driver IC for IC pin legs do tolerance test, by testing and simulation software Designer for collocation, IC to improve the degree of tolerance to ESD. Keywords: electrostatic discharge, integrated circuit (IC), electrostatic discharge protection circuit (ESD protection circuits)