| Summary: | 碩士 === 正修科技大學 === 機電工程研究所 === 102 === In semiconductor industry, they are looking forward to replacing the using of gold wire in the IC packaging due to the on-going rise of gold raw material. Owing the stability and reliability considerations, the substitutes are still inferior to gold wire. Therefore how to improve product yields and reduce costs in semiconductor industry is an important concern. In recent years, with the demands of lighter, smaller and multi-functions of electronic products, the design of Multi-Chip Module and 3-Dimensional Package in IC packaging technology is becoming very popular.For any 3-Dimensional and Multi-Chip Module layout, the direction of epoxy compound flow may not be constrained to line along the leadframe plane,owing to the layout structure of the chips. The excessive wire sag often results in crosstalk or shorting of the bond wires of the upper and lower layers.In a packaging, different layers of wire bond loops (Q-loop, S-loop and M-loop), subjected to varying amounts of drag force, can result in wire sweep and wire sag differences. This may increase the possibility of wire shorts and chips failure. Therefore, the aim of this study is to provide a systematic method to perform numerical analysis for 3-dimensional and multi-chip module (MCM) in electronic packaging by considering wire sweep and wire sag control.
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