Automatic Generation of Parameterized Layouts for Analog Building Blocks

• Main Authors: Zhi-Wen Wang, 王志文
• Other Authors: Ching-Lueh Chang
• Format: Others
• Language: zh-TW
• Online Access: http://ndltd.ncl.edu.tw/handle/64874867047499886306

碩士 === 元智大學 === 資訊工程學系 === 101 === Because traditional analog circuit elements are more sensitive and vulnerable to parasitic effects, may make the layout design is completed (Layout) can not meet specifications. Therefore, in order to reduce the number of times repeatedly redesigned to reduce design time and cost spent to improve the design efficiency. Most of the conventional analog circuit design is an artificial design, so will con-sume a lot of time, resulting in the design efficiency. In order to sensitive analog circuit design, reduce repetitive design problems, reduce design time and cost consumed in order to improve design efficiency, there is currently a kind used with parametric rep-resentation of polygon-based Layout, which will use the polygon contains parameter-ized to achieve a more flexible way to adjust the Layout component size, in this study, mainly for the efficient and automated evaluation of parasitics. Finally, in the Layout layout design is completed, you can use Boolean operators polygon operation, find the element which intersects the point of intersection and blocks, and verify the correctness containing parameters Layout.