Automatic Generation of Parameterized Layouts for Analog Building Blocks
碩士 === 元智大學 === 資訊工程學系 === 101 === Because traditional analog circuit elements are more sensitive and vulnerable to parasitic effects, may make the layout design is completed (Layout) can not meet specifications. Therefore, in order to reduce the number of times repeatedly redesigned to reduce desig...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Online Access: | http://ndltd.ncl.edu.tw/handle/64874867047499886306 |