A Sub-1V 0.18um Output-Capacitor-Free Digitally Controlled LDO

• Main Authors: Hsiang-Hsiung Chang, 張翔雄
• Other Authors: 楊維斌
• Format: Others
• Language: zh-TW
• Published: 2013
• Online Access: http://ndltd.ncl.edu.tw/handle/62588891110537999137

碩士 === 淡江大學 === 電機工程學系碩士班 === 101 === In this thesis, the concept based on low power consumption, and reducing the input voltage is become the top priority. In 0.18um process, the input voltage of 1.8V to basic, how to reduce to less 1V is an important topic in the study of normal operation. Low dropout regulator should be applied to provide a stable voltage, and the accuracy of output voltage is extremely important. So the line regulation and the load regulation will be the accuracy of the reference indicators. Therefore, the overall circuit can be divided into three parts. The first part is using SAR_Control digital signal to turn on the power transistor for achieving the output voltage. The second part is using shift register to fine tuning output voltage in order to accuracy. The third part is comparator. The size of power transistor will be important because the limit of the load current. Using 8 bit SAR_Control to drive transistor large enough for achieving the desired output voltage. The output voltage only close to the desired voltage, and it does not meet the extremely accurate. So adding 80 bit shift register to control the small size power transistor. The fine tuning range can be included in the TT,FF,SS, three kind of process, and can be meet the expected specifications. Though the above mentioned circuit design and simulation can be obtained a sub-1V Output-Capacitor-Free Digitally Controlled LDO. The input voltage is 0.7V, and output voltage is 0.5V. When the heavy load current is 20mA, the line regulation is 0.1mV / mA, and the quiescent is only 2.5uA.