A Sub-1V 0.18um Output-Capacitor-Free Digitally Controlled LDO
碩士 === 淡江大學 === 電機工程學系碩士班 === 101 === In this thesis, the concept based on low power consumption, and reducing the input voltage is become the top priority. In 0.18um process, the input voltage of 1.8V to basic, how to reduce to less 1V is an important topic in the study of normal operation. Low dr...
| Main Authors: | , |
|---|---|
| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2013
|
| Online Access: | http://ndltd.ncl.edu.tw/handle/62588891110537999137 |