3D VLSI Floorplanning
碩士 === 國立臺北科技大學 === 電機工程系所 === 101 === As the complexity of integrated circuits have grown rapidly in recent years, the interconnect delay, cost, heat and yield rate became the bottleneck of traditional 2D architecture. The emerging 3D architecture used the technique of Through-Silicon-Via (TSV), by...
| Main Authors: | , |
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| Format: | Others |
| Language: | en_US |
| Published: |
2013
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| Online Access: | http://ndltd.ncl.edu.tw/handle/mq547q |