A Constant-Lock-Cycle All-Digital Delay-Locked Loop with a Resettable Delay Line
碩士 === 國立臺灣科技大學 === 電機工程系 === 101 === With the progress of CMOS technologies, the complexity of the system on a chip (SOC) and the SOC’s operating frequency are dramatically increasing. To achieve system synchronization in an SOC in such high clock rate is an important task. Thus, a low-power high-p...
| Main Authors: | , |
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| Format: | Others |
| Language: | zh-TW |
| Published: |
2012
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| Online Access: | http://ndltd.ncl.edu.tw/handle/95970685040727785209 |