Weight-Based Device Area Allocation for Close-to-Optimum INL-Based Yield in Integrated Circuits

• Main Authors: Arif Widodo, 阿威
• Other Authors: Poki Chen
• Format: Others
• Language: en_US
• Published: 2013
• Online Access: http://ndltd.ncl.edu.tw/handle/90134590578595996865

碩士 === 國立臺灣科技大學 === 電子工程系 === 101 === In the past, analog integrated-circuit (IC) papers focused much less on the layout than design. Among those IC layout papers, most attention were paid to the layout patterns of critical devices to reduce the systematic mismatch for yield enhancement in analog integrated circuits. Even less of them focused on area allocation to minimize the impact of random mismatch for yield optimization. In 2006, an excellent layout paper dedicated for area allocation was finally presented. However, the area allocation strategies were presented in a case-by-case basis and verified by selected simulations around the optimum only. To make matters worse, no convincing theoretical deduction was given to prove the correctness of those strategies. This thesis focus on area allocation strategy based on the device weight for the close-to-optimum integral non-linearity (INL)-based yield in integrated circuits. To demonstrate this strategy, not only full-coverage simulation but also theoretical analysis of area allocations will be given for some important representative analog circuits. Moreover, a test chip of R-2R ladder circuits has been realized in a TSMC 0.35μm standard CMOS process to verify the excellence of the weight based area allocation strategy. Finally, as a byproduct, a rule of thumb for weight-based device area allocation for close-to-optimum INL-based yield will be presented to significantly ease the burden of IC designers who know not much about process variation modeling or yield estimation when facing new analog circuits.