Test Generation of Path Delay Faults Induced by Defect in Power TSV
碩士 === 國立臺灣大學 === 電子工程學研究所 === 101 === This thesis presents a novel test generation technique for defective power TSV induced path delay faults in 3D IC. This paper provides a simple close-form analysis to show that, in a regular 3D power grid model, open defects in power TSV do not induce serious...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2013
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| Online Access: | http://ndltd.ncl.edu.tw/handle/10735519149111374519 |