| Summary: | 碩士 === 國立臺灣大學 === 電子工程學研究所 === 101 === In this thesis, a 40-Gb/s receiver has been implemented in 65-nm CMOS technology, which composed of three critical components of a wireline backplane receiver – an analog equalizer, a clock and data recovery circuit (CDR), and a demultiplexer (DMUX).
The analog equalizer consists of two gain stages and two filter stages, totally providing at most 14.9-dB boosting and 4.8-dB dc gain. It compensates sufficiently for the loss of the 5-cm channel on a Rogers board, and has a 35-mV input sensitivity.
The following is a 40-Gb/s full-rate CDR, constructed with a linear phase detector (PD) and a frequency detector (FD) without an external reference clock. Both the PD and the FD operate only with the data signal and the clock signal from the voltage-controlled oscillator (VCO), and thus detect the phase error and the frequency error automatically.
The last part of the receiver is a DMUX. Like most typical structures, this DMUX is implemented with flip-flops to sample the desired output data. Further, in this design, the 40-Gb/s data is sampled by the quarter-rate clock signal and thus the DMUX produces the 10-Gb/s data signal.
This circuit occupies 1.1 × 1 mm^2 including pads, consumes 427 mW from a 1.2-V supply, and achieves BER < 10^-12 for 2^31 – 1 PRBS.
|
|---|
